The minimum maximal k-partial-matching problem

In this paper, we introduce a new problem related to bipartite graphs called minimum maximal k-partial-matching (MMKPM) which has been modelled by using a relaxation of the concept of matching in a graph. The MMKPM problem can be viewed as a generalization of the classical Hitting Set and Set Cover problems. This property has been used to prove that the MMKPM problem is NPComplete. An integer linear programming formulation and a greedy algorithm have been proposed. The problem can be applied to the design process of finite state machines with input multiplexing for simplifying the complexity of multiplexers

Minimum maximum reconfiguration cost problem

This paper discusses the problem of minimizing the reconfiguration cost of some types of reconfigurable systems. A formal definition of the problem and a proof of its NP-completeness are provided. In addition, an Integer Linear Programming formulation is proposed. The proposed problem has been used for optimizing a design stage of Finite Virtual State Machines

Finite State Machines With Input Multiplexing: A Performance Study

Finite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping FSMs into ROM memory. In this paper, we propose a new architecture for implementing FSMIMs, called FSMIM with state-based input selection, whose goal is to achieve a further reduction in memory usage. This paper also describes in detail the algorithms for generating FSMIMs used by the tool FSMIM-Gen, which has been developed and made available on the Internet for free public use. A comparative study in terms of speed and area between FSMIM approaches and other field programmable gate array-based techniques is presented. The results show that the FSMIM approaches obtain huge reductions in the look-up table (LUT) usage by using a small number of embedded memory blocks. In addition, speed improvements over conventional LUT-based implementations have been obtained in many cases

High-Performance Architecture for Binary-Tree-Based Finite State Machines

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%

Methodology for Distributed-ROM-based Implementation of Finite State Machines

This brief explores the optimization of distributed-ROM-based Finite State Machine (FSM) implementations as an alternative to conventional implementations based on Look-Up Tables (LUTs). In distributed-ROM implementations, LUTs with constant output value (called constant LUTs) and LUTs with the same content (called equivalent LUTs) can be saved. We propose a methodology to implement FSMs using distributed ROM that includes: (1) a greedy state encoding algorithm, (2) an algorithm to find the way of interconnecting the address signals to the ROM that maximize the number of constant or equivalent LUTs, and (3) a set of architectures to implement the columns of the ROM. The results obtained have been compared with conventional LUT-based implementations using standard benchmarks. The proposed technique reduces the number of LUTs in a 91% of cases and increases the speed in all cases

FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration

In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA. The proposed RAM specification has been tested with different target devices.Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Máquinas de estados finitos con multiplexión de entradas: una contribución al diseño e implementación electrónica de máquinas de estados

Esta tesis doctoral supone una contribución a la implementación electrónica de máquinas de estados finitos, en particular a la implementación mediante arquitecturas basadas en memoria. En los últimos años se ha observado un creciente interés por este tipo de arquitecturas debido principalmente al elevado número de recursos de memoria disponibles en los nuevos dispositivos FPGA. El estudio realizado tiene como objetivo mejorar las prestaciones de las implementaciones basadas en el modelo de Máquina de Estados Finitos con Multiplexión de Entradas (FSMIM, sigla del inglés Finite State Machine with Input Multiplexing), que permite aprovechar las indeterminaciones en las entradas de una máquina de estados para reducir el tamaño de la memoria requerida. Se ha propuesto una nueva arquitectura para la implementación de FSMIM que complementa a la arquitectura existente, ampliando el abanico de opciones de diseño para la implementación de máquinas de estados, lo que favorece el cumplimiento de las restricciones de diseño impuestas por la aplicación. Se han propuesto nuevos algoritmos para la generación de implementaciones de FSMIM a partir de máquinas de estados convencionales, que mejoran las prestaciones de dichas implementaciones tanto en velocidad como en consumo de recursos respecto a los algoritmos existentes. En este contexto, la contribución más importante ha sido modelar uno de los problemas de optimización que surgen en el diseño de FSMIM, probar su NP-completitud y proporcionar una formulación basada en programación lineal entera para resolverlo. Se ha realizado un estudio experimental en el que se analiza tanto el consumo de recursos como la velocidad de las implementaciones de FSMIM y de las implementaciones convencionales de máquinas de estado en dispositivos FPGA. Este estudio ha probado que las técnicas presentadas consiguen mejorar las prestaciones de las implementaciones de FSMIM. Por otra parte, respecto a las implementaciones convencionales de máquinas de estados, el estudio ha puesto de manifiesto que las implementaciones de FSMIM constituyen una alternativa viable a las implementaciones basadas en celdas lógicas y que presentan mayor velocidad y menor consumo de recursos que las basadas exclusivamente en bloques de memoria empotrados

Performance Evaluation of RAM-Based Implementation of Finite State Machines in FPGAs

This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The influence of the FSM characteristics on speed and area has been studied, taking into account the particular features of different FPGA families, like the size of LUTs, the size of memory blocks, the number of embedded multiplexer levels and the specific decoding logic for distributed RAM. Our study can be useful for efficiently implementing FPGA-based state machines

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

Synthetic generation of address-events for real-time image processing

Address-event-representation (AER) is a communication protocol that emulates the nervous system's neurons communication, and that is typically used for transferring images between chips. It was originally developed for bio-inspired and real-time image processing systems. Such systems may consist of a complicated hierarchical structure with many chips that transmit images among them in real time, while performing some processing. In this paper several software methods for generating AER streams from images stored in a computer's memory are presented. A hardware version that works in real-time is also being studied. All of them have been evaluated and compared.Comisión Europea IST-2001-34102